The latest revisions to the PCIe standard are progressing, with the specification for version 7.0 finalized in June, according to reports. This follows earlier stages of development, including version 0.9 of the 7.0 specification discussed approximately a year ago. Now, attention is turning to the next iteration, PCIe 8.0, which is currently in development (version 0.3 as of September) and being demonstrated by companies like Synopsys.
At the recent DesignCon event, held February 24-26 in Santa Clara, Synopsys showcased its initial hardware support for PCIe 8.0. The demonstration featured a PAM4 signal – already used in PCIe 7.0 – characterized by its three “eyes.” This visual representation confirms the signal’s integrity and the differentiation between the four voltage levels that define PAM4 encoding. The technology is crucial for increasing data transfer speeds in modern computing systems.
The demonstration achieved data rates of 256 GTr/s per lane, aiming for the 1 Tio/s projected by the PCI-SIG for x16 buses – double the performance of PCIe 7.0. Synopsys offers a range of solutions to support this, including controllers, physical layer interfaces, and verification tools. Notably, the demonstration utilized an existing PCIe 7.0 product that was overclocked to reach the anticipated PCIe 8.0 speeds. This approach highlights the potential for compatibility between the versions, as the PAM4 encoding remains consistent. This simplifies the upgrade path for manufacturers.
This progress suggests that compatible motherboards and add-in cards could be available in the medium term. However, the primary target applications for the protocol remain high-performance computing – such as physics and chemistry simulations, weather modeling, and artificial intelligence. While gaming typically isn’t as sensitive to these interconnects as long as sufficient video memory is available, it remains to be seen if that will still be the case by 2030.
