Rambus has unveiled a new chipset designed to enable low-power, high-performance memory modules for AI server platforms. Announced on April 22, 2026, the SOCAMM2 chipset supports JEDEC-standard LPDDR5X-based memory modules capable of operating at speeds up to 9.6 Gb/s.
The company described the SOCAMM2 as the first step in a broader roadmap of LPDDR-based server module solutions, reflecting its ongoing collaboration with industry partners to support memory architectures optimized for evolving AI workloads in data center infrastructure.
Built to improve signal and power integrity, the chipset includes integrated voltage regulators and an SPD hub to provide control, telemetry, and localized power delivery functions. These features are intended to enhance performance, reliability, and interoperability for advanced memory architectures in demanding AI server environments.
Rambus emphasized that the SOCAMM2 enables a modular, serviceable form factor for memory modules, allowing IT teams to upgrade or replace components without requiring complete system overhauls. This approach aims to reduce operational costs and minimize downtime in large-scale AI deployments.
The technology leverages the power efficiency and compact design of LPDDR memory—typically used in mobile devices—and adapts it for data center apply. By enabling detachable LPDDR5X memory modules, the chipset represents a shift from traditional soldered memory setups toward greater flexibility in managing AI-driven workloads.
According to Rambus, the SOCAMM2 chipset is already being produced by partners such as Micron and SK hynix, with memory module capacities ranging from 6 GB to 512 GB available. The company noted that future iterations may support emerging standards like LPDDR6 as part of its broader product family roadmap.
